The invention relates to the field of electronic and optoelectronic components produced on III-V material and intended to be used in the context of applications involving high data transfer rate on optical fibres.
The invention more specifically relates to the field of heterojunction bipolar transistors produced on III-V material. The object of the invention is to propose a method of manufacturing heterojunction bipolar transistors intended for manufacturing circuits for transmitting and receiving data on optical fibres, for example, or in any other high-throughput application. In order to follow changes in technology, such transistors need to be faster and faster and more and more compact.
A heterojunction bipolar transistor on III-V material is illustrated in FIG. 1. Such a transistor 1 is perfectly mastered in the state of the art. It consists of several epitaxial layers on an III-V substrate S, in the present case InP, the different layers being etched in order to form mesas which define the collector C, the base B and the emitter E of the transistor 1. Electrical contacts must be made on each of the mesas by depositing metallic regions 10, 20, 30.
A heterojunction is situated between the base and the emitter. The semiconductor layers constituting the base and the emitter are produced from different materials, the first from InGaAs and the second from InP, each doped with a different type. The heterojunction allows very high dopings of the base and makes it possible to produce a very fine base B. Thus very high operating frequencies are obtained.
According to the application, the transistor 1 can be of the simple heterojunction type (SHBT) with a homojunction between the base B and the collector C; or of the double heterojunction type (DHBT), the second heterojunction being situated between the base B and the collector C.
In order to obtain faster transistors, it is first of all necessary to decrease the size of the transistor and to reduce the parasitic surfaces extrinsic to the transistors.
In order to reduce the interconnection capacitances of the transistors, it is necessary to move them closer to each other. However, a minimum distance between two components is required in order to limit heating phenomena. In order to reduce this distance, it is therefore necessary to limit the heat dissipation of the transistors. In the case of a bipolar transistor, this heat dissipation is directly related to the surface area of the emitter. Reducing the extrinsic parasitics therefore requires decreasing the sizes of the transistors.
It should also be stated that the performance of a transistor is measured in particular at its operating frequency and depends on several parameters, including the base-collector capacitance CBC. It is therefore necessary to reduce this capacitance CBC to the maximum possible extent in order to guarantee a better operating frequency, and consequently increased speed.
A first solution consists in reducing the base-collector capacitance by selective etching. This solution is presented in the publication xe2x80x9cReduction of Base-Collector Capacitance by undercutting the Collector and Subcollector in GaInAs/InP DHBT""sxe2x80x9d by Y. Miyamoto, J. M. M. Rios, A. G. Dentai and S. Chandrasekar (ATandT Bell Laboratories), which appeared on Mar. 3, 1996 in IEEE Electron Device Letters, Vol. 17, No3.
Such a solution is illustrated in FIGS. 2a to 2c and consists essentially in partially underetching the collector layer C.
This solution has been implemented for a double heterojunction transistor (DHBT). The base layer B is composed of GaInAs and the collector layer C of InP. The latter is deposited on at least one sub-collector layer SC of GaInAs on which the contact 20 is made. The heterojunction between the base B and the collector C makes it possible to effect a selective underetching of the collector C with respect to the base B. It is therefore possible to reduce the surface area of the collector C whilst completely preserving the base B.
The capacitance CBC depends essentially on the thickness of the collector layer C and the common surface between the base B and collector C layers.
In order to reduce the capacitance CBC, this publication proposes to reduce the common base-collector surface. To this end, the collector layer C made of InP is etched selectively between the base B and sub-collector SC layers.
It should be noted that this lateral etching of the InP collector C is possible only along certain crystallographic orientations, this same etching being completely blocked along unfavourable crystallographic axes. This solution is consequently applicable only if the transistor is oriented along one of the axes [001] or [010] on an InP wafer cut in the plane {100}.
This lateral etching makes it possible to reduce the base-collector common surface, as illustrated in FIG. 2b. 
Nevertheless, when the longitudinal section of FIG. 2c is considered, it can be seen that the base-collector common surface is still large because of the surface 15 necessary for the contact 10 on the base B.
This surface area 15 is negligible for large transistors, but becomes a nuisance in the case of a small transistor, where it may represent up to 60% of the size of the transistor.
Thus the main problem related to the reduction of the size of the transistors stems from the proportional increase in the parasitic semiconductor surfaces intended for the contacts 10, 20, 30, and more specifically for the contact on the base 10. In particular, these surfaces are of a few xcexcm2. For a transistor 20 xcexcm long, these surfaces are negligible, whereas for a transistor 2 to 3 xcexcm long, these same surfaces become proportionally large and cause a degradation in the performance of the transistor.
The proportional decrease in these parasitic surfaces imposes severe technological constraints which are difficult to reconcile with the manufacturing yields imposed by the production of circuits containing several hundreds of transistors.
In order to resolve this problem of parasitic surface related to the contact on the base, the company NTT proposes a solution which consists of transferring this contact area outside the transistor itself by means of a metallic xe2x80x9cair bridgexe2x80x9d.
This solution, illustrated in FIG. 3, is disclosed in the publication xe2x80x9cHigh performance small InP/InGaAs HBTs with reduced parasitic base-collector capacitance fabricated using a novel base-metal designxe2x80x9d by Minoru Ida, Shoji Yamahata, Hiroki Nakajima, Niriyuki Watanabe (NTT Photonics laboratories) In Proc of ISCS, Berlin Aug. 22-26, 1999.
This solution has been used on a simple heterojunction transistor (SHBT), the base B and the collector C both being composed of InGaAs doped differently. A metallic bridge 105 extends the contact metal 10 of the base B towards pads 115 to allow the production of a small transistor 1 without the parasitic surface related to the contact area 10 on the base B.
The metallic air bridge 105 is oriented along the crystallographic direction [010] whilst the transistor is oriented along the direction [01-1]. This particular implantation makes it possible to obtain a speed of etching of the collector C and base B layers under the bridge 105 which are higher than on the edges of the transistor 1.
This solution requires a particular implantation of the transistor, bridge and pads which complies with the crystallographic constraints.
In addition, since the etching of the bridge 105 and the etching of the transistor 1 are carried out simultaneously, this entails a very narrow bridge width.
In addition, the contact pads 115 on the base B must be connected so as to afford a correct electrical connection.
In addition, this solution being applied to simple heterojunction bipolar transistors SHBT, the collector C cannot be underetched laterally as described previously since it is of the same nature as the base B. It is therefore necessary to provide a very narrow base in order to reduce the base-collector surface area and the capacitance CBC.
The aim of the present invention is to resolve the drawbacks of the prior art.
To this end, the invention proposes a novel method for producing a metallic air bridge without width constraints and independent of the crystallographic direction of the substrate.
The object of the present invention is more particularly a method of manufacturing a double heterojunction bipolar transistor comprising successively at least one sub-collector layer, a collector layer, a base layer and a metallic layer deposited on the said base layer; the said metallic layer being extended towards a contact pad of the base by an underetched metallic xe2x80x9cair bridgexe2x80x9d, characterised in that producing the said xe2x80x9cair bridgexe2x80x9d includes the following steps:
effecting a first localised etching under said bridge, this first etching being selective so as to etch the sub-collector layer laterally; and
effecting a second localised etching under the said bridge, this second etching being selective so as to vertically etch at least the collector layer.
According to one characteristic, the sub-collector layer is gallium indium arsenide (GaInAs).
According to one characteristic, the collector layer is indium phosphide (InP).
According to a preferential embodiment, the transistor also has a second sub-collector layer of indium phosphide, this second sub-collector layer being etched vertically during the second selective etching.
According to one characteristic, the transistor is produced on a semi-insulating indium phosphide substrate, the substrate being partly etched vertically during the second selective etching.
According to one variant embodiment, the metallic xe2x80x9cair bridgexe2x80x9d is oriented perpendicularly to a crystallographic direction favourable to the InP etching, one edge of the metallic region, one edge of the contact pad and one end of the metallic xe2x80x9cair bridgexe2x80x9d being aligned.
The present invention relates to a double heterojunction bipolar transistor having InP in the collector and a metallic region deposited on the base layer, the said metallic region extending towards a contact pad through an underetched metallic xe2x80x9cair bridgexe2x80x9d, characterised in that the said xe2x80x9cair bridgexe2x80x9d is oriented in a crystallographic direction unfavourable to the etching of the InP.
The present invention also concerns a component having a metallic region deposited on epitaxial layers on a semi-insulating substrate made of III-V material, the said metallic region extending towards a contact pad through an underetched metallic xe2x80x9cair bridgexe2x80x9d, characterised in that the component has at least one layer of InP deposited directly on the semi-insulating substrate, the said layer being etched under the metallic xe2x80x9cair bridgexe2x80x9d.
The method according to the invention has the advantage of being completely compatible with the conventional methods of manufacturing heterojunction bipolar transistors. Only the pattern of the metal of the base is modified compared with a conventional transistor.
In addition, the method according to the invention makes it possible to effect the insulation of the air bridge along any crystallographic orientation.
In addition, the capacitance CBC of the transistor according to the invention has been able to be halved compared with a conventional transistor, for an emitter surface area of 2xc3x971.2 xcexcm2; and, for the same performance level, the consumption of the transistor according to the invention has been divided by twelve.